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In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.

E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, A. Dasu, and S. Shumarayev. FPL, page 106-110. IEEE Computer Society, (2018)

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Davor Zavisic

Mark Davoren

Davor Turkovic

Davor Baros

Davor Zagorac

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Blackhole & TT-Metalium: The Standalone AI Computer and its Programming Model.J. Vasiljevic, and D. Capalija. HCS, page 1-30. IEEE, (2024)Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays.D. Capalija, and T. Abdelrahman. FPL, page 1-8. IEEE, (2014)Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor.D. Capalija, and T. Abdelrahman. IEEE Trans. Parallel Distributed Syst., 24 (2): 392-405 (2013)Compute Substrate for Software 2.0.J. Vasiljevic, L. Bajic, D. Capalija, S. Sokorac, D. Ignjatovic, L. Bajic, M. Trajkovic, I. Hamer, I. Matosevic, A. Cejkov and 34 other author(s). IEEE Micro, 41 (2): 50-55 (2021)Customizable FPGA OpenCL matrix multiply design template for deep neural networks.J. Yinger, E. Nurvitadhi, D. Capalija, A. Ling, D. Marr, K. Srivatsan, D. Moss, and S. Subhaschandra. FPT, page 259-262. IEEE, (2017)Flexibility: FPGAs and CAD in Deep Learning Acceleration.G. Chiu, A. Ling, D. Capalija, A. Bitar, and M. Abdelfattah. ISPD, page 34-41. ACM, (2018)A high-performance overlay architecture for pipelined execution of data flow graphs.D. Capalija, and T. Abdelrahman. FPL, page 1-8. IEEE, (2013)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, A. Dasu and 1 other author(s). FPL, page 106-110. IEEE Computer Society, (2018)A Multithreaded Soft Processor for SoPC Area Reduction.B. Fort, D. Capalija, Z. Vranesic, and S. Brown. FCCM, page 131-142. IEEE Computer Society, (2006)An OpenCL™ Deep Learning Accelerator on Arria 10.U. Aydonat, S. O'Connell, D. Capalija, A. Ling, and G. Chiu. FPGA, page 55-64. ACM, (2017)

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Disambiguation of "Capalija, Davor"

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In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.

Please choose a person to relate this publication to

Davor Zavisic

Mark Davoren

Davor Turkovic

Davor Baros

Davor Zagorac

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Capalija, Davor"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.

Please choose a person to relate this publication to

Davor Zavisic

Mark Davoren

Davor Turkovic

Davor Baros

Davor Zagorac

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.