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14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.

M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu, K. Chiu, G. Guglielmo, P. Mantovani, L. Piccolboni, G. Tombesi, D. Trilla, J. Wellman, E. Yang, A. Amarnath, Y. Jing, B. Mishra, J. Park, V. Suresh, S. Adve, P. Bose, D. Brooks, L. Carloni, K. Shepard, and G. Wei. ISSCC, page 262-264. IEEE, (2024)

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Sushmitha Swaminathan

Karthik Arumugam

Ashwin Swaminathan

Karthik Gururaj

Karthik Narasimhan

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Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.E. Kultursay, K. Swaminathan, V. Saripalli, V. Narayanan, M. Kandemir, and S. Datta. CODES+ISSS, page 245-254. ACM, (2012)Enabling architectural innovations using non-volatile memory.V. Narayanan, V. Saripalli, K. Swaminathan, R. Mukundrajan, G. Sun, Y. Xie, and S. Datta. ACM Great Lakes Symposium on VLSI, page 439-444. ACM, (2011)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures.K. Swaminathan, J. Kotra, H. Liu, J. Sampson, M. Kandemir, and V. Narayanan. VLSID, page 221-226. IEEE Computer Society, (2015)An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs.K. Swaminathan, H. Liu, J. Sampson, and V. Narayanan. ISCA, page 241-252. IEEE Computer Society, (2014)Energy Efficiency Boost in the AI-Infused POWER10 Processor.B. Thompto, D. Nguyen, J. Moreira, R. Bertran, H. Jacobson, R. Eickemeyer, R. Rao, M. Goulet, M. Byers, C. Gonzalez and 16 other author(s). ISCA, page 29-42. IEEE, (2021)Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms.Y. Park, S. Pal, A. Amarnath, K. Swaminathan, W. Lu, A. Buyuktosunoglu, and P. Bose. IEEE Comput. Archit. Lett., 23 (1): 108-111 (January 2024)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.M. dos Santos, T. Jia, M. Cochet, K. Swaminathan, J. Zuckerman, P. Mantovani, D. Giri, J. Zhang, E. Loscalzo, G. Tombesi and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems.S. Advani, N. Chandramoorthy, K. Swaminathan, K. Irick, Y. Cho, J. Sampson, and V. Narayanan. ICCD, page 501-504. IEEE Computer Society, (2014)BRAVO: Balanced Reliability-Aware Voltage Optimization.K. Swaminathan, N. Chandramoorthy, C. Cher, R. Bertran, A. Buyuktosunoglu, and P. Bose. HPCA, page 97-108. IEEE Computer Society, (2017)

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Disambiguation of "Swaminathan, Karthik"

Please choose a person to relate this publication to

Sushmitha Swaminathan

Karthik Arumugam

Ashwin Swaminathan

Karthik Gururaj

Karthik Narasimhan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Swaminathan, Karthik"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.

Please choose a person to relate this publication to

Sushmitha Swaminathan

Karthik Arumugam

Ashwin Swaminathan

Karthik Gururaj

Karthik Narasimhan

Other publications of authors with the same name

Disambiguation