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14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.

M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu, K. Chiu, G. Guglielmo, P. Mantovani, L. Piccolboni, G. Tombesi, D. Trilla, J. Wellman, E. Yang, A. Amarnath, Y. Jing, B. Mishra, J. Park, V. Suresh, S. Adve, P. Bose, D. Brooks, L. Carloni, K. Shepard, and G. Wei. ISSCC, page 262-264. IEEE, (2024)

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Tomas Tamberg

Friedrich Arthur Tambert

Martina Tambert

Friedrich Arthur Tambert

Katja Tamberg

Other publications of authors with the same name

A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.T. Tambe, J. Zhang, C. Hooper, T. Jia, P. Whatmough, J. Zuckerman, M. dos Santos, E. Loscalzo, D. Giri, K. Shepard and 4 other author(s). ISSCC, page 342-343. IEEE, (2023)Robomorphic computing: a design methodology for domain-specific accelerators parameterized by robot morphology.S. Neuman, B. Plancher, T. Bourgeat, T. Tambe, S. Devadas, and V. Reddi. ASPLOS, page 674-686. ACM, (2021)SM6: A 16nm System-on-Chip for Accurate and Noise-Robust Attention-Based NLP Applications : The 33rd Hot Chips Symposium - August 22-24, 2021.T. Tambe, E. Yang, G. Ko, Y. Chai, C. Hooper, M. Donato, P. Whatmough, A. Rush, D. Brooks, and G. Wei. HCS, page 1-13. IEEE, (2021)GoldenEye: A Platform for Evaluating Emerging Numerical Data Formats in DNN Accelerators.A. Mahmoud, T. Tambe, T. Aloui, D. Brooks, and G. Wei. DSN, page 206-214. IEEE, (2022)VaPr: Variable-Precision Tensors to Accelerate Robot Motion Planning.Y. Hsiao, S. Hari, B. Sundaralingam, J. Yik, T. Tambe, C. Sakr, S. Keckler, and V. Reddi. IROS, page 6304-6309. (2023)EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP.T. Tambe, C. Hooper, L. Pentecost, E. Yang, M. Donato, V. Sanh, A. Rush, D. Brooks, and G. Wei. CoRR, (2020)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference.T. Tambe, E. Yang, Z. Wan, Y. Deng, V. Reddi, A. Rush, D. Brooks, and G. Wei. DAC, page 1-6. IEEE, (2020)CAMEL: Co-Designing AI Models and eDRAMs for Efficient On-Device Learning.S. Zhang, T. Tambe, N. Cuevas, G. Wei, and D. Brooks. HPCA, page 861-875. IEEE, (2024)MASR: A Modular Accelerator for Sparse RNNs.U. Gupta, B. Reagen, L. Pentecost, M. Donato, T. Tambe, A. Rush, G. Wei, and D. Brooks. PACT, page 1-14. IEEE, (2019)

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Disambiguation of "Tambe, Thierry"

Please choose a person to relate this publication to

Tomas Tamberg

Friedrich Arthur Tambert

Martina Tambert

Friedrich Arthur Tambert

Katja Tamberg

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tambe, Thierry"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.

Please choose a person to relate this publication to

Tomas Tamberg

Friedrich Arthur Tambert

Martina Tambert

Friedrich Arthur Tambert

Katja Tamberg

Other publications of authors with the same name

Disambiguation