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14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.

M. dos Santos, T. Jia, J. Zuckerman, M. Cochet, D. Giri, E. Loscalzo, K. Swaminathan, T. Tambe, J. Zhang, A. Buyuktosunoglu, K. Chiu, G. Guglielmo, P. Mantovani, L. Piccolboni, G. Tombesi, D. Trilla, J. Wellman, E. Yang, A. Amarnath, Y. Jing, B. Mishra, J. Park, V. Suresh, S. Adve, P. Bose, D. Brooks, L. Carloni, K. Shepard, and G. Wei. ISSCC, page 262-264. IEEE, (2024)

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Shibashish Giri

Wolfgang Girisch

Philipp Girichidis

Joseph Girisch

Jana Girisch

Other publications of authors with the same name

The MosaicSim Simulator (Full Technical Report).O. Matthews, A. Manocha, D. Giri, M. Orenes-Vera, E. Tureci, T. Sorensen, T. Ham, J. Aragón, L. Carloni, and M. Martonosi. CoRR, (2020)Accelerators and Coherence: An SoC Perspective.D. Giri, P. Mantovani, and L. Carloni. IEEE Micro, 38 (6): 36-45 (2018)Agile SoC Development with Open ESP : Invited Paper.P. Mantovani, D. Giri, G. Guglielmo, L. Piccolboni, J. Zuckerman, E. Cota, M. Petracca, C. Pilato, and L. Carloni. ICCAD, page 96:1-96:9. IEEE, (2020)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.M. dos Santos, T. Jia, M. Cochet, K. Swaminathan, J. Zuckerman, P. Mantovani, D. Giri, J. Zhang, E. Loscalzo, G. Tombesi and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.F. Gao, T. Chang, A. Li, M. Orenes-Vera, D. Giri, P. Jackson, A. Ning, G. Tziantzioulis, J. Zuckerman, J. Tu and 7 other author(s). CICC, page 1-2. IEEE, (2023)PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs.B. Seyoum, D. Giri, K. Chiu, B. Natter, and L. Carloni. DATE, page 1-6. IEEE, (2023)Runtime reconfigurable memory hierarchy in embedded scalable platforms.D. Giri, P. Mantovani, and L. Carloni. ASP-DAC, page 719-726. ACM, (2019)A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.T. Jia, P. Mantovani, M. dos Santos, D. Giri, J. Zuckerman, E. Loscalzo, M. Cochet, K. Swaminathan, G. Tombesi, J. Zhang and 8 other author(s). ESSCIRC, page 269-272. IEEE, (2022)MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces.G. Eichler, L. Piccolboni, D. Giri, and L. Carloni. ICCD, page 101-108. IEEE, (2021)Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs.B. Seyoum, D. Giri, K. Chiu, and L. Carloni. CASES, page 25-26. IEEE, (2022)

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Disambiguation of "Giri, Davide"

Please choose a person to relate this publication to

Shibashish Giri

Wolfgang Girisch

Philipp Girichidis

Joseph Girisch

Jana Girisch

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Giri, Davide"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.

Please choose a person to relate this publication to

Shibashish Giri

Wolfgang Girisch

Philipp Girichidis

Joseph Girisch

Jana Girisch

Other publications of authors with the same name

Disambiguation