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Formally analyzing fault tolerance in datapath designs using equivalence checking., , , и . ASP-DAC, стр. 133-138. IEEE, (2016)Automated data analysis techniques for a modern silicon debug environment., , , и . ASP-DAC, стр. 298-303. IEEE, (2012)Post-silicon patching for verification/debugging with high-level models and programmable logic., и . ASP-DAC, стр. 232-237. IEEE, (2012)Bug Identification of a Real Chip Design by Symbolic Model Checking., , и . EDAC-ETC-EUROASIC, стр. 132-136. IEEE Computer Society, (1994)SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement., , и . J. Electron. Test., 35 (5): 655-678 (2019)Toward Unification of Synthesis and Verification in Topologically Constrained Logic Design.. Proc. IEEE, 103 (11): 2052-2060 (2015)Performance Estimation with Automatic False-Path Detection for System-Level Designs., , и . IPSJ Trans. Syst. LSI Des. Methodol., (2010)Kinetic analysis in human brain of 11C(R)-rolipram, a positron emission tomographic radioligand to image phosphodiesterase 4: A retest study and use of an image-derived input function., , , , , , , , и . NeuroImage, 54 (3): 1903-1909 (2011)High-level optimization of integer multipliers over a finite bit-width with verification capabilities., , , и . MEMOCODE, стр. 56-65. IEEE, (2009)Development and Testing of Force-Sensing Forceps Using FBG for Bilateral Micro-Operation System., , , , , , , и . IEEE Robotics Autom. Lett., 3 (4): 4281-4288 (2018)