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Accelerating Tsunami simulation with FPGA and GPU through automatic compilation.

. ACWR, page 79. ACM, (2011)

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On variable ordering of binary decision diagrams for the application of multi-level logic synthesis., , and . EURO-DAC, page 50-54. EEE Computer Society, (1991)234 scheduling of 3-2 and 2-1 eliminations for parallel image compositing using non-power-of-two number of processes., , and . HPCS, page 421-428. IEEE, (2015)RTL datapath optimization using system-level transformations., , , and . ISQED, page 309-316. IEEE, (2014)Specification and formal verification of power gating in processors., and . ISQED, page 604-610. IEEE, (2014)Early case splitting and false path detection to improve high level ATPG techniques., and . ISCAS, page 1463-1466. IEEE, (2011)Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition., , , and . IEEE Trans. Computers, 64 (6): 1579-1593 (2015)Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures., , , and . IESS, volume 231 of IFIP Advances in Information and Communication Technology, page 121-134. Springer, (2007)A new approach for selecting inputs of logic functions during debug., and . ISQED, page 166-173. IEEE, (2017)Multiple Error Diagnosis Based on Xlists., , , , and . DAC, page 660-665. ACM Press, (1999)Efficient Sum-to-One Subsets Algorithm for Logic Optimization., and . DAC, page 443-448. IEEE Computer Society Press, (1992)