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Efficient synthetic traffic models for large, complex SoCs.

, , , , and . HPCA, page 297-308. IEEE Computer Society, (2016)

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Quantifying and coping with parametric variations in 3D-stacked microarchitectures., , , , , and . DAC, page 144-149. ACM, (2010)Challenges of High-Capacity DRAM Stacks and Potential Directions., , , and . MCHPC@SC, page 4-13. ACM, (2018)A Comparison of Scalable Superscalar Processors., , and . SPAA, page 126-137. ACM, (1999)Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism., , , , , , , , and . CoRR, (2016)Cost-effective design of scalable high-performance systems using active and passive interposers., , , and . ICCAD, page 728-735. IEEE, (2017)Circuits for wide-window superscalar processors., , , and . ISCA, page 236-247. IEEE Computer Society, (2000)Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product., , , , , , and . ISCA, page 57-70. IEEE, (2021)A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction.. IEEE PACT, page 243-254. IEEE Computer Society, (2005)Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory., , , , , and . DAC, page 100. ACM, (2019)Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources., , , and . MICRO, page 1169-1181. ACM, (2021)