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Circuit optimization techniques to mitigate the effects of soft errors in combinational logic.

, , , and . ACM Trans. Design Autom. Electr. Syst., 15 (1): 5:1-5:27 (2009)

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Boloor Ramananda Rao

Bharathi Vasudeva Rao

Yadlapalli Venkateswara Rao

Balakrishna Rao

Sonti Venkata Suryanarayana Rao

 

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Soft error reduction in combinational logic using gate resizing and flipflop selection., , and . ICCAD, page 502-509. ACM, (2006)Statistical estimation of leakage current considering inter- and intra-die process variation., , , and . ISLPED, page 84-89. ACM, (2003)Circuit optimization techniques to mitigate the effects of soft errors in combinational logic., , , and . ACM Trans. Design Autom. Electr. Syst., 15 (1): 5:1-5:27 (2009)Modeling and Analysis of Parametric Yield under Power and Performance Constraints., , , and . IEEE Des. Test Comput., 22 (4): 376-385 (2005)Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 468-479 (2007)Leakage-and crosstalk-aware bus encoding for total power reduction., , , and . DAC, page 779-782. ACM, (2004)An efficient static algorithm for computing the soft error rates of combinational circuits., , , and . DATE, page 164-169. European Design and Automation Association, Leuven, Belgium, (2006)Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation., , , , , , , , , and 1 other author(s). MICRO, page 7-18. IEEE Computer Society, (2003)Logic SER Reduction through Flipflop Redesign., , , and . ISQED, page 611-616. IEEE Computer Society, (2006)An efficient surface-based low-power buffer insertion algorithm., , , , and . ISPD, page 86-93. ACM, (2005)