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Disambiguation of "Jain, Vikram"

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TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge.

, , , , , and . VLSI Technology and Circuits, page 20-21. IEEE, (2022)

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Vikram Mehta

Vikram Menon

Vikram Mavalankar

Gora Jain

Prabhat Jain

 

Other publications of authors with the same name

Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks., , and . AICAS, page 1-4. IEEE, (2021)Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication., , and . ICECS, page 45-48. IEEE, (2019)TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge., , , , , and . CoRR, (2023)Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting., , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (12): 2220-2228 (2021)Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 25-34 (2021)BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration., , , , and . HPCA, page 732-746. IEEE, (2024)Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge., , , and . ISCAS, page 1-5. IEEE, (2024)TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge., , , , , and . VLSI Technology and Circuits, page 20-21. IEEE, (2022)PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge., , , , , , , , and . DAC, page 1-6. IEEE, (2023)DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2022)