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Disambiguation of "Devanathan, V. R."

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Methodology for low power test pattern generation using activity threshold control logic.

, , and . ICCAD, page 526-529. IEEE Computer Society, (2007)

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Vasudharani Devanathan

Devanathan Raghunathan

V Saile

V Geoffroy

V Ustinov

 

Other publications of authors with the same name

Towards adaptive test of multi-core RF SoCs., , , , , and . DATE, page 743-748. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Towards effective and compression-friendly test of memory interface logic., , , and . ITC, page 124-133. IEEE Computer Society, (2010)A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems., , and . ICDCS Workshops, page 488-492. IEEE Computer Society, (2003)Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test., and . VLSI Design, page 262-267. IEEE Computer Society, (2011)PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test., , , and . ITC, page 1-9. IEEE Computer Society, (2007)Interactive presentation: On power-profiling and pattern generation for power-safe scan tests., , and . DATE, page 534-539. EDA Consortium, San Jose, CA, USA, (2007)Methodology for low power test pattern generation using activity threshold control logic., , and . ICCAD, page 526-529. IEEE Computer Society, (2007)ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs., , , , and . VLSID, page 342-347. IEEE Computer Society, (2014)Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.. Asian Test Symposium, page 300-305. IEEE Computer Society, (2005)New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation., , and . VLSID, page 363-368. IEEE Computer Society, (2015)