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Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations: Invited Paper., , , , , , , , and . IRPS, page 1-10. IEEE, (2023)Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs., , , , , , , , , and . IRPS, page 6. IEEE, (2022)Isolation of nanowires made on bulk wafers by ground plane doping., , , , , and . ESSDERC, page 300-303. IEEE, (2017)Lateral NWFET optimization for beyond 7nm nodes., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning., , , , , , , , , and 30 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)The properties, effect and extraction of localized defect profiles from degraded FET characteristics., , , , , , , , , and 1 other author(s). IRPS, page 1-7. IEEE, (2021)NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures., , , , , , , , , and . IRPS, page 2. IEEE, (2015)Reliability challenges in Forksheet Devices: (Invited Paper)., , , , , , , , , and 2 other author(s). IRPS, page 1-8. IEEE, (2023)Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors., , , , , , , and . ASICON, page 1-4. IEEE, (2019)PPAC scaling enablement for 5nm mobile SoC technology., , , , , , , , , and 7 other author(s). ESSDERC, page 240-243. IEEE, (2017)