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A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors., , , , , , , , , и 8 other автор(ы). IEEE J. Solid State Circuits, 52 (8): 2194-2207 (2017)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification., , , , , , , и . IEEE J. Solid State Circuits, 58 (11): 3266-3274 (ноября 2023)A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 59 (1): 52-64 (января 2024)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed., , , , , , , , , и 7 other автор(ы). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning., , , , , , , , , и 2 other автор(ы). ISCAS, стр. 1-5. IEEE, (2021)5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 110-112. IEEE, (2020)14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 234-236. IEEE, (2020)13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 224-226. IEEE, (2020)eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (4): 858-868 (2017)A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 496-498. IEEE, (2018)