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Disambiguation of "van Santen, Victor M."

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Special Session: Machine Learning for Semiconductor Test and Reliability.

, , , , , , , , , and . VTS, page 1-11. IEEE, (2021)

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Leo van Santen

Eric Santen

Ludger Santen

Heike Santen

Reinhard Santen

 

Other publications of authors with the same name

Special Session: Machine Learning for Semiconductor Test and Reliability., , , , , , , , , and . VTS, page 1-11. IEEE, (2021)Reliability Challenges with Self-Heating and Aging in FinFET Technology., , , , , , and . IOLTS, page 68-71. IEEE, (2019)NCFET to Rescue Technology Scaling: Opportunities and Challenges., , , , and . ASP-DAC, page 637-644. IEEE, (2020)Modeling Emerging Technologies using Machine Learning: Challenges and Opportunities., , , , and . ICCAD, page 15:1-15:9. IEEE, (2020)Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability., , , , , , , , , and . IRPS, page 6-1. IEEE, (2018)Degradation Models and Optimizations for CMOS Circuits. Karlsruhe University, Germany, (2023)base-search.net (ftubkarlsruhe:oai:EVASTAR-Karlsruhe.de:1000158506).Impact of Self-Heating on Performance, Power and Reliability in FinFET Technology., , , , , and . ASP-DAC, page 68-73. IEEE, (2020)BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array - including Sense Amplifiers and Write Drivers - under Processor Activity., , , , , , , , and . IRPS, page 1-7. IEEE, (2020)Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths., , , , , and . IRPS, page 1-6. IEEE, (2023)Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits., , , and . DFT, page 1-6. IEEE, (2023)