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Disambiguation of "Wright, John Charles"

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A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.

, , , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2721-2725 (2020)

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John Charles Fisher

John Charles Caney

John Charles Hammer

Wright Jacob

Glenn Wright

 

Other publications of authors with the same name

Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures., , , , , , , , , and 4 other author(s). CoRR, (2019)An Automated and Process-Portable Generator for Phase-Locked Loop., , , , , , , , , and 2 other author(s). DAC, page 511-516. IEEE, (2021)An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (1): 140-152 (2022)A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET., , , , , , , , , and 9 other author(s). ESSCIRC, page 259-262. IEEE, (2021)A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow., , , , , , , , and . ISCAS, page 2881-2885. IEEE, (2022)4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET., , , , , , , , , and 2 other author(s). ISSCC, page 58-60. IEEE, (2021)A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2721-2725 (2020)Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs., , , , , , , , , and 7 other author(s). IEEE Micro, 40 (4): 10-21 (2020)Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration., , , , , , , , , and 9 other author(s). DAC, page 769-774. IEEE, (2021)Invited: Chipyard - An Integrated SoC Research and Implementation Environment., , , , , , , , , and 8 other author(s). DAC, page 1-6. IEEE, (2020)