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Disambiguation of "Chiu, Pi-Feng"

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A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.

, , , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2721-2725 (2020)

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Yü Chih Chiu

Pi Huang

pi!1031782362!

Pi Ovaskainen

Chung-wai Chiu

 

Other publications of authors with the same name

Improving Noise Tolerance of Hardware Accelerated Artificial Neural Networks., , , , and . ICMLA, page 797-801. IEEE, (2018)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements., , , , , and . IEEE J. Solid State Circuits, 45 (10): 2142-2155 (2010)Non-Volatile Memory Array Based Quantization- and Noise-Resilient LSTM Neural Networks., , , , , and . ICRC, page 25-33. IEEE, (2019)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC., , , , , , , , , and 4 other author(s). ESSCIRC, page 269-272. IEEE, (2016)An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS., , , , and . VLSI Circuits, page 61-62. IEEE, (2018)Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor., , , and . A-SSCC, page 121-124. IEEE, (2016)A double-tail sense amplifier for low-voltage SRAM in 28nm technology., , and . A-SSCC, page 181-184. IEEE, (2016)A Binarized Neural Network Accelerator with Differential Crosspoint Memristor Array for Energy-Efficient MAC Operations., , , , and . ISCAS, page 1-5. IEEE, (2019)Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC., , and . ASP-DAC, page 197-203. IEEE, (2011)Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM)., , , , and . ASICON, page 299-302. IEEE, (2011)