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A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.

J. Wright, C. Schmidt, B. Keller, D. Dabbelt, J. Kwak, V. Iyer, N. Mehta, P. Chiu, S. Bailey, K. Asanovic, and B. Nikolic. IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2721-2725 (2020)

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FASED: FPGA-Accelerated Simulation and Evaluation of DRAM.D. Biancolin, S. Karandikar, D. Kim, J. Koenig, A. Waterman, J. Bachrach, and K. Asanovic. FPGA, page 330-339. ACM, (2019)Optimizing Matrix Multiply Using PHiPAC: A Portable, High-Performance, ANSI C Coding Methodology.J. Bilmes, K. Asanovic, C. Chin, and J. Demmel. International Conference on Supercomputing, page 340-347. ACM, (1997)A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET.A. Gonzalez, J. Zhao, B. Korpan, H. Genc, C. Schmidt, J. Wright, A. Biswas, A. Amid, F. Sheikh, A. Sorokin and 9 other author(s). ESSCIRC, page 259-262. IEEE, (2021)Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors.M. Zhang, and K. Asanovic. ISCA, page 336-345. IEEE Computer Society, (2005)CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems.S. Karandikar, A. Udipi, J. Choi, J. Whangbo, J. Zhao, S. Kanev, E. Lim, J. Alakuijala, V. Madduri, Y. Shao and 3 other author(s). ISCA, page 39:1-39:17. ACM, (2023)FPGA Accelerated INDEL Realignment in the Cloud.L. Wu, D. Bruns-Smith, F. Nothaft, Q. Huang, S. Karandikar, J. Le, A. Lin, H. Mao, B. Sweeney, K. Asanovic and 2 other author(s). HPCA, page 277-290. IEEE, (2019)Direction-optimizing breadth-first search.S. Beamer, K. Asanovic, and D. Patterson. SC, page 12. IEEE/ACM, (2012)FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud.S. Karandikar, H. Mao, D. Kim, D. Biancolin, A. Amid, D. Lee, N. Pemberton, E. Amaro, C. Schmidt, A. Chopra and 6 other author(s). ISCA, page 29-42. IEEE Computer Society, (2018)An Energy-Efficient RISC-V RV32IMAC Microcontroller for Periodical-Driven Sensing Applications.C. Duran, M. Wachs, L. G., A. Huntington, J. Ardila, J. Kang, A. Amaya, H. Gómez, J. Romero, L. Fernandez and 11 other author(s). CICC, page 1-4. IEEE, (2020)AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning.A. Haj-Ali, Q. Huang, W. Moses, J. Xiang, K. Asanovic, J. Wawrzynek, and I. Stoica. MLSys, mlsys.org, (2020)

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A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.

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A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.