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Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation., , , , , , и . SBCCI, стр. 1-6. IEEE, (2018)Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing., , , , , , , , и . ISCAS, стр. 1-5. IEEE, (2019)Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors., , , , , , и . IET Comput. Digit. Tech., 15 (3): 230-240 (2021)An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing., , , , , и . ICECS, стр. 1-4. IEEE, (2020)A power-predictive environment for fast and power-aware ASIC-based FIR filter design., , , , , и . SBCCI, стр. 168-173. ACM, (2017)Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors., , , , , , и . NEWCAS, стр. 309-312. IEEE, (2018)Exploring Motion Vector Cost with Partial Distortion Elimination in Sum of Absolute Differences for HEVC Integer Motion Estimation., , , , , , и . NEWCAS, стр. 1-4. IEEE, (2019)Framework-based arithmetic core generation to explore ASIC-based parallel binary multipliers., , , , и . ICECS, стр. 478-481. IEEE, (2017)Improving the Partial Product Tree Compression on Signed Radix-2m Parallel Multipliers., , , , и . NEWCAS, стр. 182-185. IEEE, (2020)Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors., , , , , , и . ICECS, стр. 486-489. IEEE, (2017)