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Disambiguation of "Devta-Prasanna, Narendra"

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Silicon evaluation of faster than at-speed transition delay tests.

, , , , , , , and . VTS, page 80-85. IEEE Computer Society, (2012)

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Narendra Kumar

Narendra Jussien

Narendra Panday

Narendra Solanki

Prasanna Rajagopalan

 

Other publications of authors with the same name

An Enhanced Logic BIST Architecture for Online Testing., , , , and . IOLTS, page 10-15. IEEE Computer Society, (2008)Multiple fault activation cycle tests for transistor stuck-open faults., , , and . ITC, page 821. IEEE Computer Society, (2010)Effective and Efficient Test Pattern Generation for Small Delay Defect., , and . VTS, page 111-116. IEEE Computer Society, (2009)Improving the Detectability of Resistive Open Faults in Scan Cells., , , , and . DFT, page 383-391. IEEE Computer Society, (2009)Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells., , , , and . DFT, page 394-402. IEEE Computer Society, (2008)Detection of Internal Stuck-open Faults in Scan Chains., , , , and . ITC, page 1-10. IEEE Computer Society, (2008)Detectability of internal bridging faults in scan chains., , , , and . ASP-DAC, page 678-683. IEEE, (2009)A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals., , , , and . ICCD, page 471-474. IEEE Computer Society, (2005)Test Generation for Open Defects in CMOS Circuits., , , , and . DFT, page 41-49. IEEE Computer Society, (2006)A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults., , , , and . ETS, page 185-192. IEEE Computer Society, (2006)