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Disambiguation of "Hiramoto, Toshiro"

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Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately.

, , , , , , , , , , , , , , , , , and . ESSDERC, page 26-29. IEEE, (2018)

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Toshiro Sugishita

 

Other publications of authors with the same name

Ultra-low-voltage operation: device perspective.. ISLPED, page 59-60. IEEE/ACM, (2011)Parallel nonvolatile programming of power-up states of SRAM cells., , , and . ASICON, page 418-421. IEEE, (2017)Emerging nanoscale silicon devices taking advantage of nanostructure physics., , and . IBM J. Res. Dev., 50 (4-5): 411-418 (2006)A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Recent Progress of Double/Dual-Gate Silicon IGBT Technologies., and . ASICON, page 1-4. IEEE, (2021)An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing., , , , , , , , and . AICAS, page 305-309. IEEE, (2020)3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat)., , , , , , , , , and 12 other author(s). ASICON, page 1137-1140. IEEE, (2017)Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs., , , , and . CICC, page 1-4. IEEE, (2011)Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers., , , , , , , , and . 3DIC, page TS9.2.1-TS9.2.4. IEEE, (2015)Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method., , , , and . NVMTS, page 1-5. IEEE, (2019)