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Disambiguation of "Ravikumar, C. P."

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Hierarchical Delay Test Generation.

, , and . J. Electron. Test., 10 (3): 231-244 (1997)

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Guido C C Clinckspoor

Thomas C C Knöbig

Guido C C Clinckspoor

Ullrich C C Jagstaidt

Thomas C C Gartenmann

 

Other publications of authors with the same name

Design of WDM Networks for Delay-Bound Multicasting., , and . HiPC, volume 1745 of Lecture Notes in Computer Science, page 399-403. Springer, (1999)Fault-tolerant routing in multiply twisted cube topology., and . J. Syst. Archit., 42 (4): 279-288 (1996)Hierarchical Delay Test Generation., , and . J. Electron. Test., 10 (3): 231-244 (1997)Improvement of ASIC Design Processes., , and . ASP-DAC/VLSI Design, page 105-. IEEE Computer Society, (2002)Incomplete Star Graph: An Economical Fault-tolerant Interconnection Network., , and . ICPP (1), page 83-90. CRC Press, (1993)A Framework for Distributed and Hierarchical Design-for-Test., , , , , and . VLSI Design, page 497-503. IEEE Computer Society, (2005)A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test., , and . ITC, page 1-10. IEEE Computer Society, (2007)Enhanced launch-off-capture transition fault testing., , and . ITC, page 10. IEEE Computer Society, (2005)On-Chip Signature Checking for Embedded Memories., , and . VLSI Design, page 558-563. IEEE Computer Society, (1998)Genetic Algorithms for Scan Path Design., and . VLSI Design, page 118-121. IEEE Computer Society, (1996)