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Disambiguation of "Ravikumar, C. P."

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A Framework for Distributed and Hierarchical Design-for-Test.

, , , , , and . VLSI Design, page 497-503. IEEE Computer Society, (2005)

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Guido C C Clinckspoor

Thomas C C Knöbig

Ullrich C C Jagstaidt

Guido C C Clinckspoor

Thomas C C Gartenmann

 

Other publications of authors with the same name

Hierarchical Delay Test Generation., , and . J. Electron. Test., 10 (3): 231-244 (1997)A Framework for Distributed and Hierarchical Design-for-Test., , , , , and . VLSI Design, page 497-503. IEEE Computer Society, (2005)A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test., , and . ITC, page 1-10. IEEE Computer Society, (2007)Enhanced launch-off-capture transition fault testing., , and . ITC, page 10. IEEE Computer Society, (2005)Design Issues in Synthesis of Reusable Cores., and . Great Lakes Symposium on VLSI, page 144-. IEEE Computer Society, (1999)Efficient Delay Test Generation for Modular Circuits., , and . Great Lakes Symposium on VLSI, page 220-. IEEE Computer Society, (1996)Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test., , and . VTS, page 167-172. IEEE Computer Society, (2007)Fault-tolerant routing in multiply twisted cube topology., and . J. Syst. Archit., 42 (4): 279-288 (1996)Genetic Algorithms for Scan Path Design., and . VLSI Design, page 118-121. IEEE Computer Society, (1996)A Novel BIST Architecture With Built-in Self Check., , and . VLSI Design, page 57-60. IEEE Computer Society, (1996)