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Disambiguation of "Levantino, Salvatore"

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A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS.

, , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Salvatore Loiero

Fundamentalmetanoia: Untersuchungen zu einem Ort eschato-praktischer Erfahrungs- und Erinnerungskultur. Uni Tübingen, habilitation, (2009)

Salvatore Cusenza

Salvatore Saputo

Salvatore Scarlata

Salvatore Grisanti

 

Other publications of authors with the same name

Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band., , , and . ISSCC, page 50-51. IEEE, (2010)Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 200-204 (2011)Time-to-digital converter with 3-ps resolution and digital linearization algorithm., , , , and . ESSCIRC, page 262-265. IEEE, (2010)2.9 A Background calibration technique to control bandwidth in digital PLLs., , , and . ISSCC, page 54-55. IEEE, (2014)10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM., , , , , , , and . ISSCC, page 188-190. IEEE, (2024)A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique., , and . ISCAS, page 1-4. IEEE, (2018)Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers., , , , , and . ISCAS, page 1-4. IEEE, (2018)A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters., , , , , , , , and . NEWCAS, page 20-24. IEEE, (2022)A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power., , , , , and . ISSCC, page 88-90. IEEE, (2011)Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter., , , , and . CICC, page 133-136. IEEE, (2006)