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A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters., , , , , , , , and . NEWCAS, page 20-24. IEEE, (2022)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , and 5 other author(s). ISSCC, page 456-458. IEEE, (2021)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter., , , , , , , , , and 4 other author(s). ISSCC, page 445-447. IEEE, (2021)A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering., , , , , , , , , and 1 other author(s). ISSCC, page 78-79. IEEE, (2023)A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter., , , and . A-SSCC, page 1-3. IEEE, (2021)Frequency synthesizers based on PLLs for cellular radio applications.. Polytechnic University of Milan, Italy, (2020)A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS., , , , , , , and . ISSCC, page 268-270. IEEE, (2019)A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching., , , , , , , , , and 3 other author(s). ISSCC, page 1-3. IEEE, (2022)A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology., , , , , , , , , and . ISSCC, page 82-83. IEEE, (2023)