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Design Understanding: From Logic to Specification*., , , , , and . VLSI-SoC, page 172-175. IEEE, (2018)Evaluating ESOP Optimization Methods in Quantum Compilation Flows., , , , and . RC, volume 11497 of Lecture Notes in Computer Science, page 191-206. Springer, (2019)Formal methods for automated debugging.. University of Bremen, Germany, (2017)Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies., , , and . DATE, page 354-359. IEEE, (2021)Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration., , , and . DAC, page 353:1-353:2. ACM, (2024)Scalable Generic Logic Synthesis: One Approach to Rule Them All., , , , , , and . DAC, page 70. ACM, (2019)Automatic Uniform Quantum State Preparation Using Decision Diagrams., , , and . ISMVL, page 170-175. IEEE, (2020)Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition., , and . DDECS, page 105-110. IEEE, (2021)A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks., , , , and . DATE, page 568-573. IEEE, (2020)Beyond local optimality of buffer and splitter insertion for AQFP circuits., , and . DAC, page 445-450. ACM, (2022)