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Evaluating ESOP Optimization Methods in Quantum Compilation Flows., , , , и . RC, том 11497 из Lecture Notes in Computer Science, стр. 191-206. Springer, (2019)Formal methods for automated debugging.. University of Bremen, Germany, (2017)Design Understanding: From Logic to Specification*., , , , , и . VLSI-SoC, стр. 172-175. IEEE, (2018)Scalable Generic Logic Synthesis: One Approach to Rule Them All., , , , , , и . DAC, стр. 70. ACM, (2019)Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies., , , и . DATE, стр. 354-359. IEEE, (2021)Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits., , и . CoRR, (2021)Safety Synthesis Sans Specification., , , , и . CoRR, (2020)Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis., , , и . ASP-DAC, стр. 395-402. IEEE, (2022)Three-Input Gates for Logic Synthesis., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle., , и . DATE, стр. 738-743. IEEE, (2020)