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Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability.

, , , , , , and . ESSDERC, page 234-237. IEEE, (2013)

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Capturing intrinsic parameter fluctuations using the PSP compact model., , , , , , , and . DATE, page 650-653. IEEE Computer Society, (2010)Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability., , , , , , and . ESSDERC, page 234-237. IEEE, (2013)Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design., , , , and . ESSDERC, page 113-116. IEEE, (2012)New reliability mechanisms in memory design for sub-22nm technologies., , , , , , , , , and 7 other author(s). IOLTS, page 111-114. IEEE Computer Society, (2011)Electrostatic Characteristics Analysis of Ferroelectric Tunneling Junctions with Different Structures., , , and . ICTA, page 112-113. IEEE, (2020)iPREFER: An Intelligent Parameter Extractor based on Features for BSIM-CMG Models., , , and . CoRR, (2024)Invited Paper: A Memristor-Based Stateful Majority-Inverter Graph Logic and 1-Bit Full Adder for In-Memory Computing Systems., , , , , and . ICTA, page 95-98. IEEE, (2023)SRAM device and cell co-design considerations in a 14nm SOI FinFET technology., , , , , , , and . ISCAS, page 2339-2342. IEEE, (2013)Multi-order Differential Neural Network for TCAD Simulation of the Semiconductor Devices., , , , , and . DAC, page 198:1-198:6. ACM, (2024)Nanowire transistor solutions for 5nm and beyond., , , , , , and . ISQED, page 269-274. IEEE, (2016)