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Disambiguation of "Li, Quincy"

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A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications.

, , , , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 170-177 (2015)

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Marie-France Quincy

Li Li

Li Li

Li Li

Li Li

 

Other publications of authors with the same name

15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications., , , , , , , , , and 2 other author(s). ISSCC, page 238-240. IEEE, (2020)12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications., , , , , , , , , and 6 other author(s). ISSCC, page 206-207. IEEE, (2017)A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 50 (1): 170-177 (2015)A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications., , , , , , , , , and 5 other author(s). ISSCC, page 316-317. IEEE, (2013)A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications., , , , , , , , , and 4 other author(s). ISSCC, page 238-239. IEEE, (2014)A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)