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15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications.

J. Chang, Y. Chen, G. Chan, H. Cheng, P. Wang, Y. Lin, H. Fujiwara, R. Lee, H. Liao, P. Wang, G. Yeap, and Q. Li. ISSCC, page 238-240. IEEE, (2020)

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Chung-Hung Liao

Jen-Jen Lin

Chenkuo Jen

Jen Kurucz

Bingzi Liao

Other publications of authors with the same name

A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications.H. Fujiwara, Y. Chen, C. Lin, W. Wu, D. Sun, S. Wu, H. Liao, and J. Chang. A-SSCC, page 185-188. IEEE, (2016)13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.Y. Chen, W. Chan, W. Wu, H. Liao, K. Pan, J. Liaw, T. Chung, Q. Li, G. Chang, C. Lin and 4 other author(s). ISSCC, page 238-239. IEEE, (2014)15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications.Q. Dong, M. Sinangil, B. Erbagci, D. Sun, W. Khwa, H. Liao, Y. Wang, and J. Chang. ISSCC, page 242-244. IEEE, (2020)An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.M. Chang, S. Shen, C. Liu, C. Wu, Y. Lin, S. Wu, C. Huang, H. Lai, Y. King, C. Lin and 3 other author(s). ISSCC, page 206-208. IEEE, (2011)A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations.H. Fujiwara, H. Mori, W. Zhao, M. Chuang, R. Naous, C. Chuang, T. Hashizume, D. Sun, C. Lee, K. Akarvardar and 8 other author(s). ISSCC, page 1-3. IEEE, (2022)A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications.J. Chang, Y. Chen, H. Cheng, W. Chan, H. Liao, Q. Li, S. Chang, S. Natarajan, R. Lee, P. Wang and 5 other author(s). ISSCC, page 316-317. IEEE, (2013)17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.H. Fujiwara, L. Wang, Y. Chen, K. Lin, D. Sun, S. Wu, J. Liaw, C. Lin, M. Chiang, H. Liao and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology.N. Akkaya, G. Chan, H. Liao, Y. Wang, and J. Chang. VLSI Technology and Circuits, page 110-111. IEEE, (2022)A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications.Y. Chen, W. Chan, W. Wu, H. Liao, K. Pan, J. Liaw, T. Chung, Q. Li, C. Lin, M. Chiang and 2 other author(s). IEEE J. Solid State Circuits, 50 (1): 170-177 (2015)An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory.M. Chang, S. Shen, C. Liu, C. Wu, Y. Lin, Y. King, C. Lin, H. Liao, Y. Chih, and H. Yamauchi. IEEE J. Solid State Circuits, 48 (3): 864-877 (2013)

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Disambiguation of "Liao, Hung-Jen"