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Measurements and Analysis of Process Variability in 90nmCMOS., and . IEEE J. Solid State Circuits, 44 (5): 1655-1663 (2009)Power and Area Minimization for Multidimensional Signal Processing., , and . IEEE J. Solid State Circuits, 42 (4): 922-934 (2007)Power - Performance Optimization for Custom Digital Circuits., and . J. Low Power Electron., 2 (1): 113-120 (2006)Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example., , and . IEEE J. Solid State Circuits, 44 (2): 569-583 (2009)A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band., , and . IEEE J. Solid State Circuits, 46 (11): 2524-2534 (2011)An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors., , , and . IEEE J. Solid State Circuits, 45 (4): 843-855 (2010)Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector., , , , and . IEEE J. Solid State Circuits, 57 (2): 573-585 (2022)A 500-Mb/s soft-output Viterbi decoder., , , and . IEEE J. Solid State Circuits, 38 (7): 1234-1241 (2003)Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI Circuits., and . IEEE J. Solid State Circuits, 58 (4): 897-900 (2023)A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2721-2725 (2020)