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Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost., , , , and . Asian Test Symposium, page 486-491. IEEE Computer Society, (2011)Thermal analysis of 8-T SRAM for nano-scaled technologies., , and . ISLPED, page 123-128. ACM, (2008)A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V., , , , , , , , , and 7 other author(s). ISSCC, page 212-214. IEEE, (2019)Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (1): 2-13 (2010)2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology., , , , , , , , , and 2 other author(s). VLSIC, page 1-2. IEEE, (2014)A high sensitivity process variation sensor utilizing sub-threshold operation., , , , and . CICC, page 125-128. IEEE, (2008)13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology., , , , , , , , , and 2 other author(s). ISSCC, page 230-231. IEEE, (2014)A leakage control system for thermal stability during burn-in test., , and . ITC, page 10. IEEE Computer Society, (2005)Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications., , and . IEEE Micro, 28 (6): 47-56 (2008)A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique., , , , , , , , , and 11 other author(s). ISSCC, page 214-216. IEEE, (2019)