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Disambiguation of "Reohr, William R."

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Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications.

, , and . IEEE Micro, 28 (6): 47-56 (2008)

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William Jórasz

William Meany

William Fisch

William Foerste

William Stewart

 

Other publications of authors with the same name

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier., , , , , , , , , and 7 other author(s). ISSCC, page 486-617. IEEE, (2007)Design SRAMs for burn-in., , , , and . VTS, page 164-170. IEEE Computer Society, (1993)Memories: Exploiting Them and Developing Them.. SoCC, page 303-310. IEEE, (2006)An on-chip dual supply charge pump system for 45nm PD SOI eDRAM., , , , , , , , , and 3 other author(s). ESSCIRC, page 66-69. IEEE, (2008)Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications., , and . IEEE Micro, 28 (6): 47-56 (2008)A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 64-75 (2011)A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache., , , , , , , , , and . ISSCC, page 342-343. IEEE, (2010)Statistical yield analysis of silicon-on-insulator embedded DRAM., , , , , , , and . ISQED, page 190-194. IEEE Computer Society, (2009)