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Disambiguation of "Mocuta, Anda"

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Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies.

, , , , , and . VLSI Design, page 697-702. IEEE Computer Society, (2005)

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Ahmad Anda

Anda Napo

László Anda

Valér anda

Muzaffer Andaç

 

Other publications of authors with the same name

Modeling FinFET metal gate stack resistance for 14nm node and beyond., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies., , , , , and . VLSI Design, page 697-702. IEEE Computer Society, (2005)CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies., , , , , , , , , and . IRPS, page 1-7. IEEE, (2019)Nonparabolicity and confinement effects of IIIV materials in novel transistors., , and . ICICDT, page 1-3. IEEE, (2015)Assessment of SiGe quantum well transistors for DRAM peripheral applications., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2015)Non-uniform strain in lattice-mismatched heterostructure tunnel field-effect transistors., , , , , , and . ESSDERC, page 412-415. IEEE, (2016)On the ballistic ratio in 14nm-Node FinFETs., , , , and . ESSDERC, page 176-179. IEEE, (2017)Dedicated technology threshold voltage tuning for 6T SRAM beyond N7., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2017)I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration., , , , , , , , , and 2 other author(s). ICICDT, page 1-4. IEEE, (2015)FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below., , , , and . ICICDT, page 1-4. IEEE, (2015)