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Disambiguation of "Cheng, Wu-Tung"

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Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data.

, , , , , , , , , , and . ATS, page 219-224. IEEE Computer Society, (2017)

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Tung-yeh Wu

Cheng-Chi Wu

Chia-Cheng Wu

Yueh-Cheng Wu

Yen-cheng Wu

 

Other publications of authors with the same name

Emulating and diagnosing IR-drop by using dynamic SDF., , , , and . ASP-DAC, page 511-516. IEEE, (2010)On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs., , , and . ETS, page 1-2. IEEE, (2014)Survey of Scan Chain Diagnosis., , , and . IEEE Des. Test Comput., 25 (3): 240-248 (2008)Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (8): 1265-1273 (2013)Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis., , , , , , , , , and 1 other author(s). ITC, page 1-9. IEEE Computer Society, (2006)Diagnosis with Limited Failure Information., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)Programmable Scan-Based Logic Built-In Self Test., , and . ATS, page 371-377. IEEE, (2007)On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation., , , and . ATS, page 103-108. IEEE, (2021)Interconnect Open Defect Diagnosis with Physical Information., , and . ATS, page 203-209. IEEE, (2006)A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders., and . IEEE Trans. Computers, 36 (7): 891-895 (1987)