( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Microscaling Data Formats for Deep Learning.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , и . CoRR, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Zhao Zhao

James Ritchie

Brian Ritchie

Ritchie Brown

Anna Ritchie

 

Другие публикации лиц с тем же именем

Building Efficient Deep Neural Networks with Unitary Group Convolutions., , , , и . CoRR, (2018)Pushing the Limits of Narrow Precision Inferencing at Cloud Scale with Microsoft Floating Point., , , , , , , , , и 14 other автор(ы). NeurIPS, (2020)Overwrite Quantization: Opportunistic Outlier Handling for Neural Network Accelerators., , и . CoRR, (2019)Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations., , , , , и . ICLR, OpenReview.net, (2020)ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests., , , , и . ICCAD, стр. 78-85. IEEE, (2015)With Shared Microexponents, A Little Shifting Goes a Long Way., , , , , , , , , и 12 other автор(ы). ISCA, стр. 83:1-83:13. ACM, (2023)Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs., , , , , , , и . FPGA, стр. 15-24. ACM, (2017)The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips., , , , , , , , , и 10 other автор(ы). IEEE Micro, 38 (2): 30-41 (2018)Microscaling Data Formats for Deep Learning., , , , , , , , , и 23 other автор(ы). CoRR, (2023)A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS., , , , , , , , , и 11 other автор(ы). VLSI Circuits, стр. 30-. IEEE, (2019)