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Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents.

, , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1739-1748 (2016)

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Daniel

Daniel

Daniel Dirkmann

In-vitro-Untersuchungen zum Effekt von Hypothermie und Azidose auf Variablen thrombelastometrischer Messungen der Blutgerinnung. Uni Duisburg-Essen, (2009)

Daniel Stanze

Systematische Analyse von Rezeptoren und Effektormechanismen der pulmonalen angeborenen Immunität. Uni Marburg, (2009)

Daniel Wied

Zivilprozessuale Qualifikationsprobleme im Spannungsfeld von Vertrag und Delikt: ein Beitrag zur Auslegung nationalen Zivilprozessrechts in europäischer Perspektive. Uni Regensburg, (2009)
 

Другие публикации лиц с тем же именем

Gate Leakage Impact on Full Open Defects in Interconnect Lines., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2209-2220 (2011)Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents., , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1739-1748 (2016)Post-bond test of Through-Silicon Vias with open defects., , и . ETS, стр. 1-6. IEEE, (2014)True Random Number Generator Based on the Variability of the High Resistance State of RRAMs., , , , , , , и . IEEE Access, (2023)Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (12): 1911-1922 (2011)Experimental Characterization of CMOS Interconnect Open Defects., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 123-136 (2008)Defective behaviours of resistive opens in interconnect lines., , и . ETS, стр. 28-33. IEEE Computer Society, (2005)Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (2): 301-312 (2013)RRAM based cell for hardware security applications., , и . IVSW, стр. 1-6. IEEE, (2016)Pre-bond testing of weak defects in TSVs., , и . IOLTS, стр. 31-36. IEEE, (2014)