( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams.

, , , и . J. Multiple Valued Log. Soft Comput., 11 (5-6): 437-465 (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Oleksiy Mishchenko

Safwat Alani

Maia Alandjiyska

Yilmaz Alan

Bertold Aland

 

Другие публикации лиц с тем же именем

A Boolean Paradigm in Multi-Valued Logic Synthesis., и . IWLS, стр. 173-177. (2002)On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis., , , , и . DATE, стр. 1649-1654. IEEE, (2019)Incremental ATPG methods for multiple faults under multiple fault models., , , и . ISQED, стр. 177-180. IEEE, (2015)Invariant-Strengthened Elimination of Dependent State Elements., , , , и . FMCAD, стр. 1-9. IEEE, (2008)NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract)., , , , , , и . BCB, стр. 623-624. ACM, (2014)Scalable min-register retiming under timing and initializability constraints., , и . DAC, стр. 534-539. ACM, (2008)Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis., , , и . ASP-DAC, стр. 395-402. IEEE, (2022)Rewriting Environment for Arithmetic Circuit Verification., , , , и . LPAR, том 57 из EPiC Series in Computing, стр. 656-666. EasyChair, (2018)Three-Input Gates for Logic Synthesis., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)A theory of nondeterministic networks., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 977-999 (2006)