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Evaluating Large Language Models Trained on Code

M. Chen, J. Tworek, H. Jun, Q. Yuan, H. Pinto, J. Kaplan, H. Edwards, Y. Burda, N. Joseph, G. Brockman, A. Ray, R. Puri, G. Krueger, M. Petrov, H. Khlaaf, G. Sastry, P. Mishkin, B. Chan, S. Gray, N. Ryder, M. Pavlov, A. Power, L. Kaiser, M. Bavarian, C. Winter, P. Tillet, F. Such, D. Cummings, M. Plappert, F. Chantzis, E. Barnes, A. Herbert-Voss, W. Guss, A. Nichol, A. Paino, N. Tezak, J. Tang, I. Babuschkin, S. Balaji, S. Jain, W. Saunders, C. Hesse, A. Carr, J. Leike, J. Achiam, V. Misra, E. Morikawa, A. Radford, M. Knight, M. Brundage, M. Murati, K. Mayer, P. Welinder, B. McGrew, D. Amodei, S. McCandlish, I. Sutskever, и W. Zaremba. arXiv:cs.LG/2107.03374. arXiv, (2021)

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Chen Chen

Shih Chen Chen

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Chen-Loung Chen

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Engineering Multifunctional Biologically-Amenable Nanomaterials for Interfacial Therapeutic Delivery and Substrate-Based Cellular Interrogation.M. Chen, B. Huang, E. Shin, E. Robinson, E. Pierstorff, H. Huang, и D. Ho. BIBE, стр. 517-523. IEEE Computer Society, (2007)Addressing social dilemmas and fostering cooperation through computer games.M. Chen. DiGRA Conference, (2005)A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation.K. Xu, F. Kuo, H. Chen, L. Cho, C. Jou, M. Chen, и R. Staszewski. IEEE J. Solid State Circuits, 54 (7): 2028-2037 (2019)Training Verifiers to Solve Math Word Problems.K. Cobbe, V. Kosaraju, M. Bavarian, M. Chen, H. Jun, L. Kaiser, M. Plappert, J. Tworek, J. Hilton, R. Nakano и 2 other автор(ы). CoRR, (2021)Scaling Laws for Autoregressive Generative Modeling.T. Henighan, J. Kaplan, M. Katz, M. Chen, C. Hesse, J. Jackson, H. Jun, T. Brown, P. Dhariwal, S. Gray и 9 other автор(ы). CoRR, (2020)When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA.H. Fan, M. Chen, L. Castelli, Z. Que, H. Li, K. Long, и W. Luk. DAC, стр. 1-6. IEEE, (2023)A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.C. Li, T. Tsai, M. Yuan, C. Liao, C. Chang, T. Huang, H. Liao, C. Lu, H. Kuo, K. Hsieh и 3 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2016)Development of a Low Cost 15-Gsps Analog-to-Digital Converter Board by using a Field Programmable Gate Array Mezzanine Card Connector for FPGA-Based Backends.H. Jiang, C. Yu, M. Chen, и M. Liu. ISIE, стр. 1345-1350. IEEE, (2019)Scale-free network of a dengue epidemic.E. Massad, S. Ma, M. Chen, C. Struchiner, N. Stollenwerk, и M. Aguiar. Appl. Math. Comput., 195 (2): 376-381 (2008)An embedded trace FCCSP substrate without glass cloth.S. Chao, C. Hung, M. Chen, Y. Lee, J. Huang, G. Kao, и D. Luh. Microelectron. Reliab., (2016)

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Evaluating Large Language Models Trained on Code

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Chen Chen

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Chen-Loung Chen

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копироватьудалитьдобавить публикацию в буферЗапись сообществапосмотреть историю данной записиURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Evaluating Large Language Models Trained on Code

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Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

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Evaluating Large Language Models Trained on Code