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Test Time Reduction in EDT Bandwidth Management for SoC Designs.

J. Janicki, M. Kassab, G. Mrugalski, N. Mukherjee, J. Rajski, and J. Tyszer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (11): 1776-1786 (2013)

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Hubertus Janicki

Kurt Janicki

Max Janicki

Paul Janicki

Jörg Janicki

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Dynamic channel allocation for higher EDT compression in SoC designs.M. Kassab, G. Mrugalski, N. Mukherjee, J. Rajski, J. Janicki, and J. Tyszer. ITC, page 265-274. IEEE Computer Society, (2010)EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.J. Janicki, J. Tyszer, A. Dutta, M. Kassab, G. Mrugalski, N. Mukherjee, and J. Rajski. ITC, page 1-9. IEEE Computer Society, (2011)Bandwidth-aware test compression logic for SoC designs.J. Janicki, J. Tyszer, G. Mrugalski, and J. Rajski. European Test Symposium, page 1-6. IEEE Computer Society, (2012)Scan Chain Diagnosis-Driven Test Response Compactor.J. Janicki, G. Mrugalski, A. Stelmach, and S. Urban. ATS, page 1-6. IEEE, (2020)High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs.M. Trawka, G. Mrugalski, N. Mukherjee, A. Pogiel, J. Rajski, J. Janicki, and J. Tyszer. ATS, page 74-80. IEEE Computer Society, (2014)EDT bandwidth management - Practical scenarios for large SoC designs.J. Janicki, J. Tyszer, W. Cheng, Y. Huang, M. Kassab, N. Mukherjee, J. Rajski, Y. Dong, and G. Giles. ITC, page 1-10. IEEE Computer Society, (2013)Test Time Reduction in EDT Bandwidth Management for SoC Designs.J. Janicki, M. Kassab, G. Mrugalski, N. Mukherjee, J. Rajski, and J. Tyszer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (11): 1776-1786 (2013)Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution.Y. Huang, J. Janicki, and S. Urban. ETS, page 1-6. IEEE, (2019)EDT Bandwidth Management in SoC Designs.J. Janicki, M. Kassab, G. Mrugalski, N. Mukherjee, J. Rajski, and J. Tyszer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (12): 1894-1907 (2012)Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.E. Moghaddam, J. Rajski, S. Reddy, and J. Janicki. Asian Test Symposium, page 267-272. IEEE Computer Society, (2011)

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Disambiguation of "Janicki, Jakub"

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Test Time Reduction in EDT Bandwidth Management for SoC Designs.

Please choose a person to relate this publication to

Hubertus Janicki

Kurt Janicki

Max Janicki

Paul Janicki

Jörg Janicki

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Janicki, Jakub"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Test Time Reduction in EDT Bandwidth Management for SoC Designs.

Please choose a person to relate this publication to

Hubertus Janicki

Kurt Janicki

Max Janicki

Paul Janicki

Jörg Janicki

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Test Time Reduction in EDT Bandwidth Management for SoC Designs.