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Disambiguation of "Hashizume, Masaki"

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On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects.

, , , , and . ISCIT, page 1-5. IEEE, (2017)

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Keiko Hashizume

Masaki Nakajima

 

Other publications of authors with the same name

On selection of adjacent lines in test pattern generation for delay faults considering crosstalk effects., , , , and . ISCIT, page 1-5. IEEE, (2017)On Delay Measurement Under Delay Variations in Boundary Scan Circuit with Embedded TDC., , and . ITC-Asia, page 169-174. IEEE, (2019)Electrical interconnect test method of 3D ICs by injected charge volume., , , and . 3DIC, page TS8.19.1-TS8.19.6. IEEE, (2015)Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes., , , and . 3DIC, page 1-5. IEEE, (2019)An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs., , and . IEICE Trans. Inf. Syst., 96-D (9): 2026-2030 (2013)SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2561-2567 (2013)Test Sequence Generation for Test Time Reduction of IDDQ Testing., , and . IEICE Trans. Inf. Syst., 87-D (3): 537-543 (2004)Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (12): 2842-2850 (2017)A test circuit for pin shorts generating oscillation in CMOS logic circuits., , , and . Syst. Comput. Jpn., 35 (13): 10-20 (2004)Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits., , and . Asian Test Symposium, page 171-176. IEEE Computer Society, (1996)