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Disambiguation of "Na, Byongwook"

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A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking.

, , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 496-498. IEEE, (2011)

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Na Wei

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Other publications of authors with the same name

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques., , , , , , , , , and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (1): 157-166 (2020)13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process., , , , , , , , , and 27 other author(s). ISSCC, page 234-236. IEEE, (2024)25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM., , , , , , , , , and 24 other author(s). ISSCC, page 346-348. IEEE, (2021)A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking., , , , , , , , , and 13 other author(s). ISSCC, page 496-498. IEEE, (2011)A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 47 (1): 107-116 (2012)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process., , , , , , , , , and 29 other author(s). ISSCC, page 382-384. IEEE, (2020)