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On Test Generation with A Limited Number of Tests.

, , and . Great Lakes Symposium on VLSI, page 12-15. IEEE Computer Society, (1999)

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Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults., , and . FTCS, page 263-270. IEEE Computer Society, (1992)A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Design of testing circuit and test generation for built-in current testing., , and . Syst. Comput. Jpn., 24 (5): 73-82 (1993)Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique., , and . Asian Test Symposium, page 94-99. IEEE Computer Society, (1996)Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits., , and . Asian Test Symposium, page 121-126. IEEE Computer Society, (1999)IDDQ Current Dependency on Test Vectors and Bridging Resistance., , and . Asian Test Symposium, page 158-163. IEEE Computer Society, (1999)An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits., , and . Asian Test Symposium, page 22-. IEEE Computer Society, (1997)A BIST Circuit for IDDQ Tests., , , , , and . Asian Test Symposium, page 390-395. IEEE Computer Society, (2003)Memory reduction of IDDQ test compaction for internal and external bridging faults., and . Asian Test Symposium, page 350-355. IEEE Computer Society, (2000)A high-speed IDDQ sensor implementation., , , and . Asian Test Symposium, page 356-361. IEEE Computer Society, (2000)