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Disambiguation of "Iwata, Hiroyuki"

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FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST.

, , , , , , , and . IEICE Trans. Inf. Syst., 103-D (11): 2289-2301 (2020)

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Hiroyuki Tan

Takashi Iwata

Hiroyuki Kobayashi

Koichiro Iwata

Hiroyuki Okamuro

 

Other publications of authors with the same name

A DFT Method for Time Expansion Model at Register Transfer Level., , and . DAC, page 682-687. IEEE, (2007)A multichannel-near-infrared-spectroscopy-triggered robotic hand rehabilitation system for stroke patients., , , , , , and . ICORR, page 158-163. IEEE, (2017)Automotive Functional Safety Assurance by POST with Sequential Observation., , , , and . IEEE Des. Test, 35 (3): 39-45 (2018)Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential Observation., , , , , , and . ATS, page 209-214. IEEE Computer Society, (2016)A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy., , , , , , and . ITC, page 1-10. IEEE, (2023)A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency., , , and . Asian Test Symposium, page 306-311. IEEE Computer Society, (2005)Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST., , , , , , and . ATS, page 155-160. IEEE, (2018)A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (9): 1535-1544 (2008)A Power Reduction Method for Scan Testing in Ultra-Low Power Designs., , and . ATS, page 141. IEEE, (2021)An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms., , , and . Asian Test Symposium, page 1. IEEE Computer Society, (2012)