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Другие публикации лиц с тем же именем

Design-for-testability for embedded delay-locked loops., и . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 984-988 (2005)Compression Technique for Interactive BIST Application., и . VTS, стр. 9-14. IEEE Computer Society, (2001)Crosstalk induced fault analysis in DRAMs., и . SoCC, стр. 171-172. IEEE, (2004)On the Reliability of the IBM MVS/XA Operating., и . IEEE Trans. Software Eng., 13 (10): 1135-1139 (1987)Optimal Logic Blocks for FPGAs, using Factorial Design Techniques., и . ICCD, стр. 470-474. IEEE Computer Society, (1994)Gate-to-channel shorts in BiCMOS logic gates., и . VTS, стр. 440-445. IEEE Computer Society, (1994)An Experimental Study Comparing 74LS181 Test Sets., , и . COMPCON, стр. 384-387. IEEE Computer Society, (1985)Embedded test control schemes for compression in SOCs., , и . DAC, стр. 679-684. ACM, (2002)Partial-Matching Technique in a Mixed-Mode BIST Environment., , и . IEEE Trans. Instrumentation and Measurement, 59 (4): 970-977 (2010)Crosstalk Induced Fault Analysis and Test in DRAMs., и . J. Electron. Test., 22 (2): 173-187 (2006)