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Novel SRAM bias control circuits for a low power L1 data cache., , , , and . NORCHIP, page 1-6. IEEE, (2012)A performance evaluation of the multiple bus network for multiprocessor systems., , , , and . SIGMETRICS, page 200-206. ACM, (1983)Dynamic Tolerance Region Computing for Multimedia., , and . IEEE Trans. Computers, 61 (5): 650-665 (2012)RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only)., , , , , and . SIGMETRICS Perform. Evaluation Rev., 39 (3): 19 (2011)Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications., , , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications., , , , and . Euro-Par (1), volume 6852 of Lecture Notes in Computer Science, page 39-51. Springer, (2011)Overlapping communication and computation by using a hybrid MPI/SMPSs approach., , , and . ICS, page 5-16. ACM, (2010)