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Disambiguation of "Joshi, Rajiv V."

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Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits.

, , , and . ISQED, page 153-158. IEEE Computer Society, (2003)

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Rajiv Trehan

Rajiv Kumar

Paneerselvam Rajiv

Jidnyasa Joshi

Rajiv Grover

 

Other publications of authors with the same name

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction., , , , , , , , , and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 23 (3): 534-543 (2015)Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction"., and . IEEE Trans. Very Large Scale Integr. Syst., 23 (7): 1380 (2015)Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices., , , , , , and . Microelectron. J., 38 (8-9): 931-941 (2007)Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives., , and . ISLPED, page 337-342. ACM, (2010)"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session)., , , and . ISLPED, page 203-206. ACM, (2000)Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design., , , , , and . ISLPED, page 263-266. ACM, (2001)14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation., , , , and . VLSIC, page 268-. IEEE, (2015)Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate., , , , , , , , , and 15 other author(s). CoRR, (2024)A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation., , , , , , , , , and 14 other author(s). DATE, page 13-16. IEEE, (2022)Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs., , and . ISCAS, page 1-5. IEEE, (2019)