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A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC.

, , , , , , и . CICC, стр. 1-2. IEEE, (2024)

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Francesco Bettella

Protein secondary structure prediction using optimized scoring functions: a comparative statistical method. FU Berlin, (2009)

Francesco Solimena

Francesco Pinosa

Francesco Knechtli

Francesco Virili

 

Другие публикации лиц с тем же именем

10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM., , , , , , , и . ISSCC, стр. 188-190. IEEE, (2024)A Novel Topology of Coupled Phase-Locked Loops., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (3): 989-997 (2021)A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 78-79. IEEE, (2023)A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique., , , , , , , , и . VLSI Technology and Circuits, стр. 1-2. IEEE, (2024)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 456-458. IEEE, (2021)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 445-447. IEEE, (2021)A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector., , , , , , и . CICC, стр. 1-2. IEEE, (2024)A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC., , , , , , и . CICC, стр. 1-2. IEEE, (2024)A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 1-3. IEEE, (2022)A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler., , , , , , , , , и 3 other автор(ы). CICC, стр. 1-2. IEEE, (2022)