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Disambiguation of "Castoro, Giacomo"

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A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector.

, , , , , , and . CICC, page 1-2. IEEE, (2024)

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Giacomo Ricciarelli

Giacomo D'Antonio

Giacomo Fornari

Giacomo Gazzaniga

Giacomo D'Antonio

 

Other publications of authors with the same name

A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering., , , , , , , , , and 1 other author(s). ISSCC, page 78-79. IEEE, (2023)10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM., , , , , , , and . ISSCC, page 188-190. IEEE, (2024)A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector., , , , , , and . CICC, page 1-2. IEEE, (2024)A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC., , , , , , and . CICC, page 1-2. IEEE, (2024)A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering., , , , , , , , and . IEEE J. Solid State Circuits, 58 (12): 3320-3337 (December 2023)10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion., , , , , , , , and . ISSCC, page 198-200. IEEE, (2024)A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology., , , , , , , , , and . ISSCC, page 82-83. IEEE, (2023)Phase Noise Analysis of Periodically ON/OFF Switched Oscillators., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (1): 54-63 (January 2023)