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Circuit models for the co-simulation of superconducting quantum computing systems., , , , , , , and . DATE, page 968-973. IEEE, (2021)High-k Dielectrics and Metal Gates for Future Generation Memory Devices, , , , , , , , , and 28 other author(s). ECS Transactions, 19 (1): 29--40 (2009)Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors., , , , , , , , , and 2 other author(s). IRPS, page 10. IEEE, (2022)Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements., , , , , , , , , and 7 other author(s). VLSI Technology and Circuits, page 230-231. IEEE, (2022)Uniform Spin Qubit Devices with Tunable Coupling in an All-Silicon 300 mm Integrated Process., , , , , , , , , and 5 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)Doped GeSe materials for selector applications., , , , , , , , , and 1 other author(s). ESSDERC, page 168-171. IEEE, (2017)Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry., , , , , , , , and . ESSCIRC, page 63-66. IEEE, (2021)Selectors for high density crosspoint memory arrays: Design considerations, device implementations and some challenges ahead., , and . ICICDT, page 1-4. IEEE, (2015)Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C-V technique., , , , and . Microelectron. Reliab., 47 (4-5): 508-512 (2007)Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing., , , , , , , , , and 19 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)