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When prefetching improves/degrades performance., , , and . Conf. Computing Frontiers, page 342-352. ACM, (2005)New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors., , , , , and . IBM J. Res. Dev., 47 (5-6): 653-670 (2003)Optimizing pipelines for power and performance., , , , , , and . MICRO, page 333-344. ACM/IEEE Computer Society, (2002)3D stacking of high-performance processors., , , , , , , , , and . HPCA, page 500-511. IEEE Computer Society, (2014)Industrial Perspectives: The Next Roadblocks in SOC Evolution: On-Chip Storage Capacity and Off-Chip Bandwidth.. HPCA, page 201-201. IEEE Computer Society, (2006)The End of Scaling? Revolutions in Technology and Microarchitecture as We Pass the 90 Nanometer Node.. ISCA, page 128. IEEE Computer Society, (2006)Integrated Analysis of Power and Performance for Pipelined Microprocessors., , , , , , and . IEEE Trans. Computers, 53 (8): 1004-1016 (2004)Duplicon Cache: Mitigating Off-Chip Memory Bank and Bank Group Conflicts Via Data Duplication., , , , and . MICRO, page 285-297. IEEE Computer Society, (2018)Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications., , and . IEEE Micro, 28 (6): 47-56 (2008)Early-Stage Definition of LPX: A Low Power Issue-Execute Processor., , , , , , , , , and 6 other author(s). PACS, volume 2325 of Lecture Notes in Computer Science, page 1-17. Springer, (2002)