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Reducing the pressure on routing resources of FPGAs with generic logic chains.

, , , и . FPGA, стр. 237-246. ACM, (2011)

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Paul Brisken

Magnus Briskorn

Rudolf Briske

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Robert Briske

 

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Path scheduling on digital microfluidic biochips., и . DAC, стр. 26-35. ACM, (2012)Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving., , и . ACM Great Lakes Symposium on VLSI, стр. 459-462. ACM, (2017)Reducing the pressure on routing resources of FPGAs with generic logic chains., , , и . FPGA, стр. 237-246. ACM, (2011)Reducing the cost of floating-point mantissa alignment and normalization in FPGAs., , , , , и . FPGA, стр. 255-264. ACM, (2012)MPSoC Design Using Application-Specific Architecturally Visible Communication., , , и . HiPEAC, том 5409 из Lecture Notes in Computer Science, стр. 183-197. Springer, (2009)Exploiting fast carry-chains of FPGAs for designing compressor trees., , и . FPL, стр. 242-249. IEEE, (2009)Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions., , , и . IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 62-75 (2014)A Low-Cost Field-Programmable Pin-Constrained Digital Microfluidic Biochip., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (11): 1657-1670 (2014)Automatic Application of Power Analysis Countermeasures., , , , , и . IEEE Trans. Computers, 64 (2): 329-341 (2015)Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage., , , , и . ACM Trans. Archit. Code Optim., 11 (2): 15:1-15:26 (2014)